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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1995 copyright ? intel corporation, 1995 order number: 290207-010 28f010 1024k (128k x 8) cmos flash memory y flash electrical chip-erase e 1 second typical chip-erase y quick pulse programming algorithm e10 m s typical byte-program e 2 second chip-program y 100,000 erase/program cycles y 12.0v g 5% v pp y high-performance read e 65 ns maximum access time y cmos low power consumption e 10 ma typical active current e50 m a typical standby current e 0 watts data retention power y integrated program/erase stop timer y command register architecture for microprocessor/microcontroller compatible write interface y noise immunity features e g 10% v cc tolerance e maximum latch-up immunity through epi processing y etox tm nonvolatile flash technology e eprom-compatible process base e high-volume manufacturing experience y jedec-standard pinouts e 32-pin plastic dip e 32-lead plcc e 32-lead tsop (see packaging spec., order y 231369) y extended temperature options intel's 28f010 cmos flash memory offers the most cost-effective and reliable alternative for read/write random access nonvolatile memory. the 28f010 adds electrical chip-erasure and reprogramming to familiar eprom technology. memory contents can be rewritten: in a test socket; in a prom-programmer socket; on- board during subassembly test; in-system during final test; and in-system after-sale. the 28f010 increases memory flexibility, while contributing to time and cost savings. the 28f010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of 8 bits. intel's 28f010 is offered in 32-pin plastic dip or 32-lead plcc and tsop packages. pin assignments conform to jedec standards for byte-wide eproms. extended erase and program cycling capability is designed into intel's etox (eprom tunnel oxide) process technology. advanced oxide processing, an optimized tunneling structure, and lower electric field combine to extend reliable cycling beyond that of traditional eeproms. with the 12.0v v pp supply, the 28f010 performs 100,000 erase and program cycles well within the time limits of the quick pulse programming and quick erase algorithms. intel's 28f010 employs advanced cmos circuitry for systems requiring high-performance access speeds, low power consumption, and immunity to noise. its 65 nanosecond access time provides no-wait-state perform- ance for a wide range of microprocessors and microcontrollers. maximum standby current of 100 m a trans- lates into power savings when the device is deselected. finally, the highest degree of latch-up protection is achieved through intel's unique epi processing. prevention of latch-up is provided for stresses up to 100 ma on address and data pins, from b 1v to v cc a 1v. with intel's etox process base, the 28f010 builds on years of eprom experience to yield the highest levels of quality, reliability, and cost-effectiveness.
28f010 290207 1 figure 1. 28f010 block diagram table 1. pin description symbol type name and function a 0 a 16 input address inputs for memory addresses. addresses are internally latched during a write cycle. dq 0 dq 7 input/output data input/output: inputs data during memory write cycles; outputs data during memory read cycles. the data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. data is internally latched during a write cycle. ce y input chip enable: activates the device's control logic, input buffers, decoders and sense amplifiers. ce y is active low; ce y high deselects the memory device and reduces power consumption to standby levels. oe y input output enable: gates the devices output through the data buffers during a read cycle. oe y is active low. we y input write enable: controls writes to the control register and the array. write enable is active low. addresses are latched on the falling edge and data is latched on the rising edge of the we y pulse. note: with v pp s 6.5v, memory contents cannot be altered. v pp erase/program power supply for writing the command register, erasing the entire array, or programming bytes in the array. v cc device power supply (5v g 10%) v ss ground nc no internal connection to device. pin may be driven or left floating. 2
28f010 28f010 290207 2 290207 3 290207 17 290207 18 figure 2. 28f010 pin configurations 3
28f010 applications the 28f010 flash memory provides nonvolatility along with the capability to perform over 100,000 electrical chip-erasure/reprogram cycles. these fea- tures make the 28f010 an innovative alternative to disk, eeprom, and battery-backed static ram. where periodic updates of code and data-tables are required, the 28f010's reprogrammability and non- volatility make it the obvious and ideal replacement for eprom. primary applications and operating systems stored in flash eliminate the slow disk-to-dram download process. this results in dramatic enhancement of performance and substantial reduction of power consumptio n e a consideration particularly impor- tant in portable equipment. flash memory increases flexibility with electrical chip erasure and in-system update capability of operating systems and applica- tion code. with updatable code, system manufactur- ers can easily accommodate last-minute changes as revisions are made. in diskless workstations and terminals, network traf- fic reduces to a minimum and systems are instant- on. reliability exceeds that of electromechanical media. often in these environments, power interrup- tions force extended re-boot periods for all net- worked terminals. this mishap is no longer an issue if boot code, operating systems, communication pro- tocols and primary applications are flash-resident in each terminal. for embedded systems that rely on dynamic ram/ disk for main system memory or nonvolatile backup storage, the 28f010 flash memory offers a solid state alternative in a minimal form factor. the 28f010 provides higher performance, lower power consumption, instant-on capability, and allows an ``execute in place'' memory hierarchy for code and data table reading. additionally, the flash memory is more rugged and reliable in harsh environments where extreme temperatures and shock can cause disk-based systems to fail. the need for code updates pervades all phases of a system's life e from prototyping to system manufac- ture to after-sale service. the electrical chip-erasure and reprogramming ability of the 28f010 allows in- circuit alterability; this eliminates unnecessary han- dling and less-reliable socketed connections, while adding greater test, manufacture, and update flexi- bility. material and labor costs associated with code changes increases at higher levels of system inte- gration e the most costly being code updates after sale. code ``bugs'', or the desire to augment system functionality, prompt after-sale code updates. field revisions to eprom-based code requires the re- moval of eprom components or entire boards. with the 28f010, code updates are implemented locally via an edge-connector, or remotely over a commun- cation link. for systems currently using a high-density static ram/battery configuration for data accumulation, flash memory's inherent nonvolatility eliminates the need for battery backup. the concern for battery failure no longer exists, an important consideration for portable equipment and medical instruments, both requiring continuous performance. in addition, flash memory offers a considerable cost advantage over static ram. flash memory's electrical chip erasure, byte pro- grammability and complete nonvolatility fit well with data accumulation and recording needs. electrical chip-erasure gives the designer a ``blank slate'' in which to log or record data. data can be periodically off-loaded for analysis and the flash memory erased producing a new ``blank slate''. a high degree of on-chip feature integration simpli- fies memory-to-processor interfacing. figure 4 de- picts two 28f010s tied to the 80c186 system bus. the 28f010's architecture minimizes interface cir- cuitry needed for complete in-circuit updates of memory contents. the outstanding feature of the tsop (thin small outline package) is the 1.2 mm thickness. with stan- dard and reverse pin configurations, tsop reduces the number of board layers and overall volume nec- essary to layout multiple 28f010s. tsop is particu- larly suited for portable equipment and applications requiring large amounts of flash memory. figure 3 illustrates the tsop serpentine layout. with cost-effective in-system reprogramming, ex- tended cycling capability, and true nonvolatility, the 28f010 offers advantages to the alternatives: eproms, eeproms, battery backed static ram, or disk. eprom-compatible read specifications, straight-forward interfacing, and in-circuit alterability offers designers unlimited flexibility to meet the high standards of today's designs. 4
28f010 figure 3. tsop serpentine layout 290207 21 5
28f010 290207 4 figure 4. 28f010 in a 80c186 system principles of operation flash-memory augments eprom functionality with in-circuit electrical erasure and reprogramming. the 28f010 introduces a command register to manage this new functionality. the command register allows for: 100% ttl-level control inputs; fixed power sup- plies during erasure and programming; and maxi- mum eprom compatibility. in the absence of high voltage on the v pp pin, the 28f010 is a read-only memory. manipulation of the external memory-control pins yields the standard eprom read, standby, output disable, and intelli- gent identifier operations. the same eprom read, standby, and output disable operations are available when high voltage is ap- plied to the v pp pin. in addition, high voltage on v pp enables erasure and programming of the device. all functions associated with altering memory con- tentseintelligent identifier, erase, erase verify, pro- gram, and program verifyeare accessed via the command register. commands are written to the register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for programming or erase operations. with the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or out- put data for erase and program verification. integrated stop timer successive command write cycles define the dura- tions of program and erase operations; specifically, the program or erase time durations are normally terminated by associated program or erase verify commands. an integrated stop timer provides simpli- fied timing control over these operations; thus elimi- nating the need for maximum program/erase timing specifications. programming and erase pulse dura- tions are minimums only. when the stop timer termi- nates a program or erase operation, the device en- ters an inactive state and remains inactive until re- ceiving the appropriate verify or reset command. write protection the command register is only active when v pp is at high voltage. depending upon the application, the system designer may choose to make the v pp pow- er supply switchableeavailable only when memory updates are desired. when v pp e v ppl , the con- 6
28f010 table 2. 28f010 bus operations mode v pp (1) a 0 a 9 ce y oe y we y dq 0 dq 7 read v ppl a 0 a 9 v il v il v ih data out output disable v ppl xxv il v ih v ih tri-state read-only standby v ppl xxv ih x x tri-state intelligent identifier (mfr) (2) v ppl v il v id (3) v il v il v ih data e 89h intelligent identifier (device) (2) v ppl v ih v id (3) v il v il v ih data e b4h read v pph a 0 a 9 v il v il v ih data out (4) read/write output disable v pph xxv il v ih v ih tri-state standby (5) v pph xxv ih x x tri-state write v pph a 0 a 9 v il v ih v il data in (6) notes: 1. refer to dc characteristics. when v pp e v ppl memory contents can be read but not written or erased. 2. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 3. all other addresses low. 3. v id is the intelligent identifier high voltage. refer to dc characteristics. 4. read operations with v pp e v pph may access array data or the intelligent identifier codes. 5. with v pp at high voltage, the standby current equals i cc a i pp (standby). 6. refer to table 3 for valid data-in during a write operation. 7. x can be v il or v ih . tents of the register default to the read command, making the 28f010 a read-only memory. in this mode, the memory contents cannot be altered. or, the system designer may choose to ``hardwire'' v pp , making the high voltage supply constantly available. in this case, all command register func- tions are inhibited whenever v cc is below the write lockout voltage v lko . (see power up/down protec- tion) the 28f010 is designed to accommodate ei- ther design practice, and to encourage optimization of the processor-memory interface. the two-step program/erase write sequence to the command register provides additional software write protections. bus operations read the 28f010 has two control functions, both of which must be logically active, to obtain data at the out- puts. chip-enable (ce y ) is the power control and should be used for device selection. output-enable (oe y ) is the output control and should be used to gate data from the output pins, independent of de- vice selection. refer to ac read timing waveforms. when v pp is high (v pph ), the read operation can be used to access array data, to output the intelligent identifier codes, and to access data for program/ erase verification. when v pp is low (v ppl ), the read operation can only access the array data. output disable with oe y at a logic-high level (v ih ), output from the device is disabled. output pins are placed in a high- impedance state. standby with ce y at a logic-high level, the standby opera- tion disables most of the 28f010's circuitry and sub- stantially reduces device power consumption. the outputs are placed in a high-impedance state, inde- pendent of the oe y signal. if the 28f010 is dese- lected during erasure, programming, or program/ erase verification, the device draws active current until the operation is terminated. intelligent identifier operation the intelligent identifier operation outputs the manu- facturer code (89h) and device code (b4h). pro- gramming equipment automatically matches the de- vice with its proper erase and programming algo- rithms. 7
28f010 with ce y and oe y at a logic low level, raising a9 to high voltage v id (see dc characteristics) acti- vates the operation. data read from locations 0000h and 0001h represent the manufacturer's code and the device code, respectively. the manufacturer- and device-codes can also be read via the command register, for instances where the 28f010 is erased and reprogrammed in the tar- get system. following a write of 90h to the com- mand register, a read from address location 0000h outputs the manufacturer code (89h). a read from address 0001h outputs the device code (b4h). write device erasure and programming are accomplished via the command register, when high voltage is ap- plied to the v pp pin. the contents of the register serve as input to the internal state-machine. the state-machine outputs dictate the function of the device. the command register itself does not occupy an ad- dressable memory location. the register is a latch used to store the command, along with address and data information needed to execute the command. the command register is written by bringing we y to a logic-low level (v il ), while ce y is low. addresses are latched on the falling edge of we y , while data is latched on the rising edge of the we y pulse. stan- dard microprocessor write timings are used. refer to ac write characteristics and the erase/ programming waveforms for specific timing parameters. command definitions when low voltage is applied to the v pp pin, the con- tents of the command register default to 00h, en- abling read-only operations. placing high voltage on the v pp pin enables read/ write operations. device operations are selected by writing specific data patterns into the command reg- ister. table 3 defines these 28f010 register commands. table 3. command definitions command cycles req'd bus first bus cycle second bus cycle operation (1) address (2) data (3) operation (1) address (2) data (3) read memory 1 write x 00h read intelligent identifier 3 write ia 90h read ia id codes (4) set-up erase/erase (5) 2 write x 20h write x 20h erase verify (5) 2 write ea a0h read x evd set-up program/program (6) 2 write x 40h write pa pd program verify (6) 2 write x c0h read x pvd reset (7) 2 write x ffh write x ffh notes: 1. bus operations are defined in table 2. 2. ia e identifier address: 00h for manufacturer code, 01h for device code. ea e erase address: address of memory location to be read during erase verify. pa e program address: address of memory location to be programmed. addresses are latched on the falling edge of the we y pulse. 3. id e identifier data: data read from location ia during device identification (mfr e 89h, device e b4h). evd e erase verify data: data read from location ea during erase verify. pd e program data: data to be programmed at location pa. data is latched on the rising edge of we y . pvd e program verify data: data read from location pa during program verify. pa is latched on the program command. 4. following the read int e ligent id command, two read operations access manufacturer and device codes. 5. figure 6 illustrates the quick erase algorithm. 6. figure 5 illustrates the quick pulse programming algorithm. 7. the second bus cycle must be followed by the desired command register write. 8
28f010 read command while v pp is high, for erasure and programming, memory contents can be accessed via the read command. the read operation is initiated by writing 00h into the command register. microprocessor read cycles retrieve array data. the device remains enabled for reads until the command register con- tents are altered. the default contents of the register upon v pp pow- er-up is 00h. this default value ensures that no spu- rious alteration of memory contents occurs during the v pp power transition. where the v pp supply is hard-wired to the 28f010, the device powers-up and remains enabled for reads until the command-regis- ter contents are changed. refer to the ac read characteristics and waveforms for specific timing parameters. intelligent identifier command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacturer- and device-codes must be ac- cessible while the device resides in the target sys- tem. prom programmers typically access signature codes by raising a9 to a high voltage. however, mul- tiplexing high voltage onto address lines is not a de- sired system-design practice. the 28f010 contains an intelligent identifier opera- tion to supplement traditional prom-programming methodology. the operation is initiated by writing 90h into the command register. following the com- mand write, a read cycle from address 0000h re- trieves the manufacturer code of 89h. a read cycle from address 0001h returns the device code of b4h. to terminate the operation, it is necessary to write another valid command into the register. set-up erase/erase commands set-up erase is a command-only operation that stages the device for electrical erasure of all bytes in the array. the set-up erase operation is performed by writing 20h to the command register. to commence chip-erasure, the erase command (20h) must again be written to the register. the erase operation begins with the rising edge of the we y pulse and terminates with the rising edge of the next we y pulse (i.e., erase-verify command). this two-step sequence of set-up followed by execu- tion ensures that memory contents are not acciden- tally erased. also, chip-erasure can only occur when high voltage is applied to the v pp pin. in the absence of this high voltage, memory contents are protected against erasure. refer to ac erase characteristics and waveforms for specific timing parameters. erase-verify command the erase command erases all bytes of the array in parallel. after each erase operation, all bytes must be verified. the erase verify operation is initiated by writing a0h into the command register. the address for the byte to be verified must be supplied as it is latched on the falling edge of the we y pulse. the register write terminates the erase operation with the rising edge of its we y pulse. the 28f010 applies an internally-generated margin voltage to the addressed byte. reading ffh from the addressed byte indicates that all bits in the byte are erased. the erase-verify command must be written to the command register prior to each byte verification to latch its address. the process continues for each byte in the array until a byte does not return ffh data, or the last address is accessed. in the case where the data read is not ffh, another erase operation is performed. (refer to set-up erase/erase). verification then resumes from the address of the last-verified byte. once all bytes in the array have been verified, the erase step is com- plete. the device can be programmed. at this point, the verify operation is terminated by writing a valid command (e.g. program set-up) to the command register. figure 6, the quick erase algorithm, illus- trates how commands and bus operations are com- bined to perform electrical erasure of the 28f010. refer to ac erase characteristics and waveforms for specific timing parameters. set-up program/program commands set-up program is a command-only operation that stages the device for byte programming. writing 40h into the command register performs the set-up operation. once the program set-up operation is performed, the next we y pulse causes a transition to an active programming operation. addresses are internally latched on the falling edge of the we y pulse. data is internally latched on the rising edge of the we y pulse. the rising edge of we y also begins the pro- gramming operation. the programming operation terminates with the next rising edge of we y , used to write the program-verify command. refer to ac programming characteristics and waveforms for specific timing parameters. 9
28f010 program-verify command the 28f010 is programmed on a byte-by-byte basis. byte programming may occur sequentially or at ran- dom. following each programming operation, the byte just programmed must be verified. the program-verify operation is initiated by writing c0h into the command register. the register write terminates the programming operation with the ris- ing edge of its we y pulse. the program-verify oper- ation stages the device for verification of the byte last programmed. no new address information is latched. the 28f010 applies an internally-generated margin voltage to the byte. a microprocessor read cycle outputs the data. a successful comparison between the programmed byte and true data means that the byte is successfully programmed. programming then proceeds to the next desired byte location. figure 5, the 28f010 quick pulse programming algorithm, il- lustrates how commands are combined with bus op- erations to perform byte programming. refer to ac programming characteristics and waveforms for specific timing parameters. reset command a reset command is provided as a means to safely abort the erase- or program-command sequences. following either set-up command (erase or program) with two consecutive writes of ffh will safely abort the operation. memory contents will not be altered. a valid command must then be written to place the device in the desired state. extended erase/program cycling eeprom cycling failures have always concerned users. the high electrical field required by thin oxide eeproms for tunneling can literally tear apart the oxide at defect regions. to combat this, some sup- pliers have implemented redundancy schemes, re- ducing cycling failures to insignificant levels. howev- er, redundancy requires that cell size be doublede an expensive solution. intel has designed extended cycling capability into its etox flash memory technology. resulting im- provements in cycling reliability come without in- creasing memory cell size or complexity. first, an advanced tunnel oxide increases the charge carry- ing ability ten-fold. second, the oxide area per cell subjected to the tunneling electric field is one-tenth that of common eeproms, minimizing the probabili- ty of oxide defects in the region. finally, the peak electric field during erasure is approximately 2 mv/cm lower than eeprom. the lower electric field greatly reduces oxide stress and the probability of failure. the 28f010 is capable or 100,000 program/erase cycles. the device is programmed and erased using intel's quick pulse programming and quick erase algorithms. intel's algorithmic approach uses a se- ries of operations (pulses), along with byte verifica- tion, to completely and reliably erase and program the device. for further information, see reliability report rr-60. quick pulse programming algorithm the quick pulse programming algorithm uses pro- gramming operations of 10 m s duration. each opera- tion is followed by a byte verification to determine when the addressed byte has been successfully pro- grammed. the algorithm allows for up to 25 pro- gramming operations per byte, although most bytes verify on the first or second operation. the entire sequence of programming and byte verification is performed with v pp at high voltage. figure 5 illus- trates the quick pulse programming algorithm. quick erase algorithm intel's quick erase algorithm yields fast and reliable electrical erasure of memory contents. the algo- rithm employs a closed-loop flow, similar to the quick pulse programming algorithm, to simulta- neously remove charge from all bits in the array. erasure begins with a read of memory contents. the 28f010 is erased when shipped from the factory. reading ffh data from the device would immedi- ately be followed by device programming. for devices being erased and reprogrammed, uni- form and reliable erasure is ensured by first pro- gramming all bits in the device to their charged state (data e 00h). this is accomplished, using the quick pulse programming algorithm, in approximately two seconds. erase execution then continues with an initial erase operation. erase verification (data e ffh) begins at address 0000h and continues through the array to the last address, or until data other than ffh is en- countered. with each erase operation, an increasing number of bytes verify to the erased state. erase efficiency may be improved by storing the address of the last byte verified in a register. following the next erase operation, verification starts at that stored ad- dress location. erasure typically occurs in one sec- ond. figure 6 illustrates the quick erase algorithm. 10
28f010 290207 5 bus command comments operation standby wait for v pp ramp to v pph (1) initialize pulse-count write set-up data e 40h program write program valid address/data standby duration of program operation (t whwh1 ) write program (2) data e c0h; stops program verify operation (3) standby t whgl read read byte to verify programming standby compare data output to data expected write read data e 00h, resets the register for read operations standby wait for v pp ramp to v ppl (1) notes: 1. see dc characteristics for the value of v pph and v ppl . 2. program verify is only performed after byte program- ming. a final read/compare may be performed (option- al) after the register is written with the read command. 3. refer to principles of operation. 4. caution: the algorithm must be followed to ensure proper and reliable operation of the de- vice. figure 5. 28f010 quick pulse programming algorithm 11
28f010 290207 6 bus command comments operation entire memory must e 00h before erasure use quick pulse programming algorithm (figure 5) standby wait for v pp ramp to v pph (1) initialize addresses and pulse-count write set-up data e 20h erase write erase data e 20h standby duration of erase operation (t whwh2 ) write erase (2) addr e byte to verify; verify data e a0h; stops erase operation (3) standby t whgl read read byte to verify erasure standby compare output to ffh increment pulse-count write read data e 00h, resets the register for read operations standby wait for v pp ramp to v ppl (1) 1. see dc characteristics for the value of v pph and v ppl . 2. erase verify is performed only after chip-erasure. a final read/compare may be performed (optional) after the register is written with the read command. 3. refer to principles of operation. 4. caution: the algorithm must be followed to ensure proper and reliable operation of the de- vice. figure 6. 28f010 quick erase algorithm 12
28f010 design considerations two-line output control flash-memories are often used in larger memory ar- rays. intel provides two read-control inputs to ac- commodate multiple memory connections. two-line control provides for: a. the lowest possible memory power dissipation and, b. complete assurance that output bus contention will not occur. to efficiently use these two control inputs, an ad- dress-decoder output should drive chip-enable, while the system's read signal controls all flash- memories and other parallel memories. this assures that only enabled memory devices have active out- puts, while deselected devices maintain the low power standby condition. power supply decoupling flash-memory power-switching characteristics re- quire careful device decoupling. system designers are interested in three supply current (i cc ) issuese standby, active, and transient current peaks pro- duced by falling and rising edges of chip-enable. the capacitive and inductive loads on the device outputs determine the magnitudes of these peaks. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 m f ceramic capacitor connected between v cc and v ss , and between v pp and v ss . place the high-frequency, low-inherent-inductance capacitors as close as possible to the devices. also, for every eight devices, a 4.7 m f electrolytic capaci- tor should be placed at the array's power supply connection, between v cc and v ss . the bulk capaci- tor will overcome voltage slumps caused by printed- circuit-board trace inductance, and will supply charge to the smaller capacitors as needed. v pp trace on printed circuit boards programming flash-memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the v pp power sup- ply trace. the v pp pin supplies the memory cell cur- rent for programming. use similar trace widths and layout considerations given the v cc power bus. ad- equate v pp supply traces and decoupling will de- crease v pp voltage spikes and overshoots. power up/down protection the 28f010 is designed to offer protection against accidental erasure or programming during power transitions. upon power-up, the 28f010 is indifferent as to which power supply, v pp or v cc , powers up first. power supply sequencing is not required. inter- nal circuitry in the 28f010 ensures that the com- mand register is reset to the read mode on power up. a system designer must guard against active writes for v cc voltages above v lko when v pp is active. since both we y and ce y must be low for a com- mand write, driving either to v ih will inhibit writes. the control register architecture provides an added level of protection since alteration of memory con- tents only occurs after successful completion of the two-step command sequences. 28f010 power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash nonvolatility increases the usable battery life of your system because the 28f010 does not consume any power to retain code or data when the system is off. table 4 illustrates the power dissipated when updating the 28f010. table 4. 28f010 typical update power dissipation (4) operation notes power dissipation (watt-seconds) array program/program verify 1 0.171 array erase/erase verify 2 0.136 one complete cycle 3 0.478 notes: 1. formula to calculate typical program/program verify power e [ v pp c y bytes c typical y prog pulses (t whwh1 c i pp2 typical a t whgl c i pp4 typical) ] a [ v cc c y bytes c typical y prog pulses (t whwh1 c i cc2 typical a t whgl c i cc4 typical ] . 2. formula to calculate typical erase/erase verify power e [ v pp (v pp3 typical c t erase typical a i pp5 typical c t whgl c y bytes) ] a [ v cc (i cc3 typical c t erase typical a i cc5 typical c t whgl c y bytes) ] . 3. one complete cycle e array preprogram a array erase a program. 4. ``typicals'' are not guaranteed, but based on a limited number of samples from production lots. 13
28f010 absolute maximum ratings * operating temperature during read 0 cto a 70 c (1) during erase/program 0 cto a 70 c (1) operating temperature during read b 40 cto a 85 c (2) during erase/program b 40 cto a 85 c (2) temperature under bias b 10 cto a 80 c (1) temperature under bias b 50 cto a 95 c (2) storage temperature b 65 cto a 125 c voltage on any pin with respect to ground b 2.0v to a 7.0v (3) voltage on pin a 9 with respect to ground b 2.0v to a 13.5v (3, 4) v pp supply voltage with respect to ground during erase/program b 2.0v to a 14.0v (3, 4) v cc supply voltage with respect to ground b 2.0v to a 7.0v (3) output short circuit current100 ma (5) notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol parameter limits unit min max t a operating temperature (1) 070 c t a operating temperature (2) b 40 a 85 c v cc v cc supply voltage (10%) (6) 4.50 5.50 v v cc v cc supply voltage (5%) (7) 4.75 5.25 v notes: 1. operating temperature is for commercial product as defined by this specification. 2. operating temperature is for extended temperature products as defined by this specification. 3. minimum dc input voltage is b 0.5v. during transitions, inputs may undershoot to b 2.0v for periods less than 20 ns. maximum dc voltage on output pins is v cc a 0.5v, which may overshoot to v cc a 2.0v for periods less than 20 ns. 4. maximum dc voltage on a 9 or v pp may overshoot to a 14.0v for periods less than 20 ns. 5. output shorted for no more than one second. no more than one output shorted at a time. 6. see high speed ac input/output reference waveforms and high speed ac testing load circuits for testing characteristics. 7. see ac input/output reference waveforms and ac testing load circuits for testing characteristics. dc characteristicsettl/nmos compatibleecommercial products symbol parameter notes limits unit test conditions min typical (4) max i li input leakage current 1 g 1.0 m av cc e v cc max v in e v cc or v ss i lo output leakage current 1 g 10 m av cc e v cc max v out e v cc or v ss i ccs v cc standby current 1 0.3 1.0 ma v cc e v cc max ce y e v ih i cc1 v cc active read current 1 10 30 ma v cc e v cc max, ce y e v il f e 6 mhz, i out e 0ma 14
28f010 dc characteristicsettl/nmos compatibleecommercial products (continued) symbol parameter notes limits unit test conditions min typical (4) max i cc2 v cc programming current 1, 2 1.0 10 ma programming in progress i cc3 v cc erase current 1, 2 5.0 15 ma erasure in progress i cc4 v cc program verify current 1, 2 5.0 15 ma v pp e v pph program verify in progress i cc5 v cc erase verify current 1, 2 5.0 15 ma v pp e v pph erase verify in progress i pps v pp leakage current 1 g 10 m av pp s v cc i pp1 v pp read current 1 90 200 m av pp l v cc or standby current g 10.0 v pp s v cc i pp2 v pp programming current 1, 2 8.0 30 ma v pp e v pph programming in progress i pp3 v pp erase current 1, 2 6.0 30 ma v pp e v pph erasure in progress i pp4 v pp program verify current 1, 2 2.0 5.0 ma v pp e v pph program verify in progress i pp5 v pp erase verify current 1, 2 2.0 5.0 ma v pp e v pph erase verify in progress v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc a 0.5 v v ol output low voltage 0.45 v v cc e v cc min i ol e 5.8 ma v oh1 output high voltage 2.4 v v cc e v cc min i oh eb 2.5 ma v id a 9 intelligent identifer voltage 11.50 13.00 v i id a 9 intelligent identifier current 1, 2 90 200 m aa 9 e v id v ppl v pp during read-only 0.00 6.5 v note: erase/program are operations inhibited when v pp e v ppl v pph v pp during read/write 11.40 12.60 v operations v lko v cc erase/write lock voltage 2.5 v dc characteristicsecmos compatibleecommercial products symbol parameter notes limits unit test conditions min typical (4) max i li input leakage current 1 g 1.0 m av cc e v cc max v in e v cc or v ss i lo output leakage current 1 g 10 m av cc e v cc max v out e v cc or v ss i ccs v cc standby current 1 50 100 m av cc e v cc max ce y e v cc g 0.2v i cc1 v cc active read current 1 10 30 ma v cc e v cc max, ce y e v il f e 6 mhz, i out e 0ma 15
28f010 dc characteristicsecmos compatibleecommercial products (continued) symbol parameter notes limits unit test conditions min typical (4) max i cc2 v cc programming current 1, 2 1.0 10 ma programming in progress i cc3 v cc erase current 1, 2 5.0 15 ma erasure in progress i cc4 v cc program verify current 1, 2 5.0 15 ma v pp e v pph , program verify in progress i cc5 v cc erase verify current 1, 2 5.0 15 ma v pp e v pph , erase verify in progress i pps v pp leakage current 1 g 10 m av pp s v cc i pp1 v pp read current, id 1 90 200 m av pp l v cc current or standby current g 10 v pp s v cc i pp2 v pp programming 1, 2 8.0 30 ma v pp e v pph current programming in progress i pp3 v pp erase current 1, 2 6.0 30 ma v pp e v pph erasure in progress i pp4 v pp program verify 1, 2 2.0 5.0 ma v pp e v pph , program current verify in progress i pp5 v pp erase verify 1, 2 2.0 5.0 ma v pp e v pph , erase current verify in progress v il input low voltage b 0.5 0.8 v v ih input high voltage 0.7 v cc v cc a 0.5 v v ol output low voltage 0.45 v v cc e v cc min i ol e 5.8 ma v oh1 output high voltage 0.85 v cc v v cc e v cc min, i oh eb 2.5 ma v oh2 v cc b 0.4 v cc e v cc min, i oh eb 100 m a v id a 9 intelligent identifier 11.50 13.00 v voltage i id a 9 intelligent identifier 1, 2 90 200 m aa 9 e v id current v ppl v pp during read-only 0.00 6.5 v note: erase/programs are operations inhibited when v pp e v ppl v pph v pp during read/write 11.40 12.60 v operations v lko v cc erase/write lock 2.5 v voltage 16
28f010 dc characteristicsettl/nmos compatibleeextended temperature products symbol parameter notes limits unit test conditions min typical (4) max i li input leakage current 1 g 1.0 m av cc e v cc max v in e v cc or v ss i lo output leakage current 1 g 10 m av cc e v cc max v out e v cc or v ss i ccs v cc standby current 1 0.3 1.0 ma v cc e v cc max ce y e v ih i cc1 v cc active read current 1 10 30 ma v cc e v cc max, ce y e v il f e 6 mhz, i out e 0ma i cc2 v cc programming current 1, 2 1.0 30 ma programming in progress i cc3 v cc erase current 1, 2 5.0 30 ma erasure in progress i cc4 v cc program verify current 1, 2 5.0 30 ma v pp e v pph program verify in progress i cc5 v cc erase verify current 1, 2 5.0 30 ma v pp e v pph erase verify in progress i pps v pp leakage current 1 g 10 m av pp s v cc i pp1 v pp read current 1 90 200 m av pp l v cc or standby current g 10.0 v pp s v cc i pp2 v pp programming current 1, 2 8.0 30 ma v pp e v pph programming in progress i pp3 v pp erase current 1, 2 6.0 30 ma v pp e v pph erasure in progress i pp4 v pp program verify current 1, 2 2.0 5.0 ma v pp e v pph program verify in progress i pp5 v pp erase verify current 1, 2 2.0 5.0 ma v pp e v pph erase verify in progress v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc a 0.5 v v ol output low voltage 0.45 v v cc e v cc min i ol e 5.8 ma v oh1 output high voltage 2.4 v v cc e v cc min i oh eb 2.5 ma v id a 9 intelligent identifer voltage 11.50 13.00 v i id a 9 intelligent identifier current 1, 2 90 500 m aa 9 e v id v ppl v pp during read-only 0.00 6.5 v note: erase/program are operations inhibited when v pp e v ppl v pph v pp during read/write 11.40 12.60 v operations v lko v cc erase/write lock voltage 2.5 v 17
28f010 dc characteristicsecmos compatibleeextended temperature products symbol parameter notes limits unit test conditions min typical (4) max i li input leakage 1 g 1.0 m av cc e v cc max current v in e v cc or v ss i lo output leakage 1 g 10 m av cc e v cc max current v out e v cc or v ss i ccs v cc standby 1 50 100 m av cc e v cc max current ce y e v cc g 0.2v i cc1 v cc active read 1 10 30 ma v cc e v cc max, ce y e v il current f e 10 mhz, i out e 0ma i cc2 v cc programming 1, 2 1.0 10 ma programming in progress current i cc3 v cc erase current 1, 2 5.0 30 ma erasure in progress i cc4 v cc program verify 1, 2 5.0 30 ma v pp e v pph current program verify in progress i cc5 v cc erase verify 1, 2 5.0 30 ma v pp e v pph current erase verify in progress i pps v pp leakage current 1 g 10 m av pp s v cc i pp1 v pp read current, 1 90 200 m av pp l v cc id current or g 10 v pp s v cc standby current i pp2 v pp programming 1, 2 8.0 30 ma v pp e v pph current programming in progress i pp3 v pp erase current 1, 2 6.0 30 ma v pp e v pph erasure in progress i pp4 v pp program verify 1, 2 2.0 5.0 ma v pp e v pph current program verify in progress i pp5 v pp erase verify 1, 2 2.0 5.0 ma v pp e v pph current erase verify in progress v il input low voltage b 0.5 0.8 v v ih input high voltage 0.7 v cc v cc a 0.5 v v ol output low voltage 0.45 v v cc e v cc min i ol e 5.8 ma v oh1 output high voltage 0.85 v cc v v cc e v cc min i oh eb 2.5 ma v oh2 v cc b 0.4 v cc e v cc min i oh eb 100 m a v id a 9 intelligent identifer 11.50 13.00 v voltage i id a 9 intelligent identifier 1, 2 90 500 m aa 9 e v id current 18
28f010 dc characteristicsecmos compatibleeextended temperature products (continued) symbol parameter notes limits unit test conditions min typical (4) max v ppl v pp during read-only 0.00 6.5 v note: erase/programs are operations inhibited when v pp e v ppl v pph v pp during read/write 11.40 12.60 v operations v lko v cc erase/write lock 2.5 v voltage capacitance t a e 25 c, f e 1.0 mhz symbol parameter notes limits unit conditions min max c in address/control capacitance 3 8 pf v in e 0v c out output capacitance 3 12 pf v out e 0v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc e 5.0v, v pp e 12.0v, t e 25 c. these currents are valid for all product versions (packages and speeds). 2. not 100% tested: characterization data available. 3. sampled, not 100% tested. 4. ``typicals'' are not guaranteed, but based on a limited number of samples from production lots. 19
28f010 ac testing input/output waveform (1) 290207 7 ac test inputs are driven at v oh (2.4 v ttl ) for a logic ``1'' and v ol (0.45 v ttl ) for a logic ``0''. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output tim- ing ends at v ih and v il . input rise and fall times (10% to 90%) k 10 ns. high speed ac testing input/output waveform (2) 290207 8 ac test inputs are driven at 3.0v for a logic ``1'' and 0.0v for a logic ``0''. input timing begins, and output timing ends, at 1.5v. input rise and fall times (10% to 90%) k 10 ns. ac testing load circuit (1) c l e 100 pf c l includes jig capacitance 290207 22 r l e 3.3 k x high speed ac testing load circuit (2) c l e 30 pf c l includes jig capacitance 290207 23 r l e 3.3 k x ac test conditions (1) input rise and fall times (10% to 90%) 10 ns input pulse levels 0.45v and 2.4v input timing reference level 0.8v and 2.0v output timing reference level 0.8v and 2.0v capacitive load100 pf high-speed ac test conditions (2) input rise and fall times (10% to 90%) 10 ns input pulse levels 0.0v and 3.0v input timing reference level 1.5v output timing reference level 1.5v capacitive load30 pf notes: 1. testing characteristics for 28f010-65 in standard configuration, and 28f010-90, 28f010-120, and 28f010-150. 2. testing characteristics for 28f010-65 in high speed configuration. 20
28f010 ac characteristicseread only operationsecommercial and extended temperature products versions v cc g 5% 28f010-65 (4) unit v cc g 10% 28f010-65 (5) 28f010-90 (5) 28f010-120 (5) 28f010-150 (5) symbol characteristic notes min max min max min max min max min max t avav /t rc read cycle time 65 70 90 120 150 ns t elqv /t ce ce y access time 65 70 90 120 150 ns t avqv /t acc address access time 65 70 90 120 150 ns t glqv /t oe oe y access time 25 28 35 50 55 ns t elqx /t lz ce y to low z 2, 3 0 0 0 0 0 ns t ehqz chip disable to output 2 35 40 45 55 55 ns in high z t glqx /t olz oe y to output 2, 3 0 0 0 0 0 ns in low z t ghqz /t df output disable to output 2 30 30 30 30 35 ns in high z t oh output hold from address, 1, 2 0 0 0 0 0 ns ce y ,oroe y change t whgl write recovery time 6 6 6 6 6 m s before read notes: 1. whichever occurs first. 2. sampled, not 100% tested. 3. guaranteed by design. 4. see high speed ac input/output reference waveforms and high speed ac testing load circuits for testing characteristics. 5. see ac input/output reference waveforms and ac testing load circuits for testing characteristics. 21
28f010 figure 7. ac waveforms for read operations 290207 9 22
28f010 ac characteristicsewrite/erase/program only operations (1) e commercial and extended temperature products versions v cc g 5% 28f010-65 (4) unit v cc g 10% 28f010-65 (5) 28f010-90 (5) 28f010-120 (5) 28f010-150 (5) symbol characteristic notes min max min max min max min max min max t avav /t wc write cycle time 65 70 90 120 150 ns t avwl /t as address set-up time 0 0 0 0 0 ns t wlax /t ah address hold time 40 40 40 40 40 ns 655 t dvwh /t ds data set-up time 40 40 40 40 40 ns 655 t whdx /t dh data hold time 10 10 10 10 10 ns t whgl write recovery time 6 6 6 6 6 m s before read t ghwl read recovery time 2 0 0 0 0 0 ns before write t elwl /t cs chip enable set-up time 15 15 15 15 15 ns before write t wheh /t ch chip enable hold time 0 0 0 0 0 ns t wlwh /t wp write pulse width 40 40 40 60 60 ns 655 t whwl /t wph write pulse width high 20 20 20 20 20 ns t whwh1 duration of programming 3 10 10 10 10 10 m s operation t whwh2 duration of erase 3 9.5 9.5 9.5 9.5 9.5 ms operation t vpel v pp set-up time to 2 1 1 1 1 1 m s chip enable low notes: 1. read timing characteristics during read/write operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. guaranteed by design. 3. the integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification. 4. see high speed ac input/output reference waveforms and high speed ac testing load circuits for testing characteristics. 5. see ac input/output reference waveforms and ac testing load circuits for testing characteristics. 6. minimum specification for extended temperature product. 23
28f010 290207 13 figure 8. typical programming capability 290207 14 figure 9. typical program time at 12v 290207 15 figure 10. typical erase capability 290207 16 figure 11. typical erase time at 12v 24
28f010 figure 12. ac waveforms for programming operations 290207 10 25
28f010 figure 13. ac waveforms for erase operations 290207 11 26
28f010 ac characteristicsealternative ce y -controlled writesecommercial and extended temperature versions v cc g 5% 28f010-65 (2, 4) unit v cc g 10% 28f010-65 (5) 28f010-90 (5) 28f010-120 (5) 28f010-150 (5) symbol characteristic notes min max min max min max min max min max t avav write cycle time 65 70 90 120 150 ns t avel address set-up time 0 0 0 0 0 ns t elax address hold time 45 45 45 55 55 ns 660 t dveh data set-up time 35 35 35 45 45 ns 650 t ehdx data hold time 10 10 10 10 10 ns t ehgl write recovery time 6 6 6 6 6 m s before read t ghwl read recovery time 2 0 0 0 0 0 ns before write t wlel write enable set-up time 0 0 0 0 0 ns before chip enable t ehwh write enable hold time 0 0 0 0 0 ns t eleh write pulse width 45 45 45 70 70 ns 660 t ehel write pulse width high 20 20 20 20 20 ns t eheh1 duration of programming 3 10 10 10 10 10 m s operation t eheh2 duration of erase 3 9.5 9.5 9.5 9.5 9.5 ms operation t vpel v pp set-up time to chip 2 1 1 1 1 1 m s enable low note: 1. read timing characteristics during read/write operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. guaranteed by design. 3. the integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification. 4. see high speed ac input/output reference waveforms and high speed ac testing load circuits for testing characteristics. 5. see ac input/output reference waveforms and ac testing load circuits for testing characteristics. 6. minimum specification for extended temperature product. 27
28f010 erase and programming performance parameter notes min typical max unit chip erase time 1, 3, 4 1 10 sec chip program time 1, 2, 4 2 12.5 sec notes: 1. ``typicals'' are not guaranteed, but based on samples from production lots. data taken at 25 c, 12.0v v pp . 2. minimum byte programming time excluding system overhead is 16 m sec (10 m sec program a 6 m sec write recovery), while maximum is 400 m sec/byte (16 m sec x 25 loops allowed by algorithm). max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. 3. excludes 00h programming prior to erasure. 4. excludes system level overhead. 28
28f010 note: alternative ce y -controlled write timings also apply to erase operations. figure 14. alternate ac waveforms for programming operations 290207 19 29
28f010 ordering information 290207 20 valid combinations: p28f010-65 n28f010-65 tn28f010-90 p28f010-90 n28f010-90 p28f010-120 n28f010-120 p28f010-150 n28f010-150 E28F010-65 f28f010-65 te28f010-90 e28f010-90 f28f010-90 tf28f010-90 e28f010-120 f28f010-120 e28f010-150 f28f010-150 additional information order number er-20, ``etox flash memory technology'' 294005 er-24, ``intel flash memory'' 294008 er-28, ``etox iii flash memory technology'' 294012 rr-60, ``etox flash memory reliability data summary'' 293002 ap-316, ``using flash memory for in-system reprogrammable nonvolatile storage'' 292046 ap-325 ``guide to flash memory reprogramming'' 292059 revision history number description 007 removed 200 ns speed bin revised erase maximum pulse count for figure 5 from 3000 to 1000 clarified ac and dc test conditions added ``dimple'' to f tsop package corrected serpentine layout 008 corrected ac waveforms added extended temperature options 009 added 28f010-65 and 28f010-90 speeds revised symbols, i.e., ce ,oe , etc. to ce y ,oe y , etc. 010 completion of read operation table labelling of program time in erase/program table textual changes or edits corrected erase/program times 30

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